1. Field of the Invention
The present invention relates to a semiconductor memory device and method of manufacturing the same, and more particularly, to a Static Random Access Memory cell capable of enhancing cell ratio and a manufacturing method thereof.
2. Description of the Related Art
A semiconductor memory device is classified into a dynamic random access memory (DRAM) and a static random access memory (SRAM) according to its method of storing data. SPAM is particular significant due to its high speed, low power consumption, and simple operation. In addition, unlike the DRAM, the SRAM has advantage of an easy design as well as not having to regularly refresh stored data.
In general, SRAM cell includes: two driving transistors which are pull-down devices; two access devices; and two pull-up devices. The SRAM cell is further classified as a full CMOS cell, a high road resistor(HRL) cell, or a thin film transistor (TFT) cell according to the type of the pull-up devices used.
The full CMOS cell utilizes a P-channel bulk MOSFET as the pull-up device. The HRL cell utilizes a polysilicon having a high resistance value as the pull-up device, and TFT cell utilizes P-channel polysilicon TFT as the pull-up device. Of the above-mentioned structures, the SRAM cell with the full CMOS cell structure has optimal operational device properties and can be fabricated with a simple process. It, however, has both NMOS and PMOS transistors in the unit cell, resulting in a large cell size. Therefore, it is applied to the memory device having a small capacitance. On the other hand, SRAM cells with the HRL cell and the TFT cell structures have relatively poor performance and is complicated in their fabrication. Because of their smaller cell size, however they are generally applied to semiconductor memory device in cases of larger capacitance.
FIG. 1 is a conventional circuit diagram of an SRAM cell with the full CMOS cell structure.
As shown in this diagram, sources S1 and S2 of PMOS transistors Q1 and Q2 for use in pull-up devices are connected to VDD. Drains D1 and D2 of the PMOS transistors Q1 and Q2 are respectively connected in series to each drains D3 and D4 of NMOS transistors Q3 and Q4 for use in pull-down devices at nodes N1 and N2. Sources S3 and S4 of the NMOS transistors Q3 and Q4 are connected to VSS. Gates G1 and G2 of the PMOS transistors Q1 and Q2 are respectively connected to gates G3 and G4 of the NMOS transistors Q3 and Q4, and these connection points thereof are respectively cross-coupled with the nodes N1, N2. In NMOS transistors Q5 and Q6 for use in access devices, gates G5 and G6 are connected to a word line W/L, sources S5 and S6 are respectively connected to bit lines B/L1 and B/L2. Drains D5 and DG of NMOS transistors Q5 and Q6 are respectively connected to the drains D3 and D4 of the NMOS transistors Q3 and Q4 at the nodes N1, N2.
In the above described SRAM cell, the NMOS transistors Q5 and Q6 are turned on by turning on the word line W/L, to store data in a HIGH state in the node N1 and data in a LOW state in the node N2. Data in a HIGH state is inputted to the bit line B/L1 and data in a LOW state is inputted to the bit line B/L2, so that the PMOS transistor Q1 and NMOS transistor Q4 are turned on, and PMOS transistor Q2 and NMOS transistor Q3 are turned off. Therefore, the node N1 becomes a HIGH state and the node N2 becomes a LOW state. Furthermore, although the word line W/L is turned off, the node N2 is latched to maintain a LOW state and the node Ni is maintained at a HIGH state.. Accordingly, data is stored in the nodes N1 and N2 respectively.
Meanwhile, one of the factors determining the characteristics of the SRAM is the current driving capability ratio of the pull down device, otherwise known as the driving device and the access device (I.sub.DSAT DRIVER TRANSISTOR /I.sub.DSAT ACCESS TRANSISTOR), otherwise known as cell ratio. A higher cell ratio results in improved performance of the SRAM. Therefore when the current amount of the pull down device is large and the current amount access device is small, the performance of the SRAM cell is improved.
An operation of the SRAM related to the cell ratio is as follows. In case the data in a low state is stored in the node N1 and the data in a high state is stored in the node N2, the voltage of the node N1 is determined by the current amount ratio of the NMOS transistors Q5 and Q6 for use in access devices and the NMOS transistors Q3 and Q4 for use in pull down devices. Accordingly, the node N1 is intended to maintain the low voltage with the increase of the current amount of the NMOS transistors Q3 and Q4, and with the decrease of that of the NMOS transistors Q5 and Q6. If so, the voltage of the node N1 is not drastically changed from the low state when the NMOS transistors Q5 and Q6 are turned on during the reading operation, even though the voltage of the bit line B/L1 is changed. In case the voltage variation of the node N1 is small, the voltage of the cross-coupled node N2 is still maintained in the high state.
Therefore, conventionally, the cell ratio is controlled in a manner wherein width of the NMOS transistor for use in access device is reduced and its length is increased to thereby reduce its the current amount, and width of the NMOS transistor for use in pull-down device is increased and its length is reduced to thereby increase its the current amount. The width and length of the transistor, however, cannot be reduced below a predetermined level, and therefore there is a restriction in reducing the size of the cell to enhance the cell ratio.